# Sources and educational limits

Original procedural 3D model and connection/tour implementation: [Ben Dicken, bddicken/nvidia](https://github.com/bddicken/nvidia). BEP adapts it with the author's permission as reported by the user: “He said it ok to use it. Just credit him.” The upstream repository has no license file; this permission is not represented as an upstream open-source license.

Public hardware facts were checked on 12 October 2026 against:

- [NVIDIA Vera CPU](https://www.nvidia.com/en-us/data-center/vera-cpu/): Olympus cores and threads, LPDDR5X/SOCAMM memory, CPU workloads, and NVLink-C2C coherent memory.
- [Inside the NVIDIA Vera Rubin Platform](https://developer.nvidia.com/blog/inside-the-nvidia-rubin-platform-six-new-chips-one-ai-supercomputer/): superchip and compute-tray composition, HBM4, NVLink, and infrastructure networking.

Bandwidth labels are published peak specifications, including bidirectional interconnect figures. They are not measured transfer speeds and are not encoded in animation timing. A logical path does not imply a mandatory software data flow, physical trace, or exact connection routing.

Dimensions, component placements, board details, floorplans, cooling plumbing, and boot/management connections are approximate or stylized, based on public imagery and the upstream author's notes. This is an educational model, not an engineering specification or performance simulation.

The CPU-focused adaptation presents the superchip and NVL72 compute tray. It does not use HGX NVL8 aggregate specifications; NVIDIA's [HGX page](https://www.nvidia.com/en-us/data-center/hgx/) currently lists system totals that differ from simple sums of the individual GPU specifications.

Upstream reference photos were copyrighted local-study resources and are omitted. Upstream `og.png` is omitted and replaced with BEP artwork. Third-party dependency notices must remain available with the distributed app; Three.js is MIT. The upstream Saira font is not redistributed by this adaptation.